Exploiting Nanoelectronic Properties of Memory Chips for Prevention of IC Counterfeiting

Authors: Supriya Chakraborty, Tamoghno Das, Manan Suri
Published: 2022-09-09

Source: https://arxiv.org/abs/2209.09197

PDF: https://arxiv.org/pdf/2209.09197

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機械学習 メモリ管理手法 IC偽造防止手法

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Abstract

This study presents a methodology for anticounterfeiting of Non-Volatile Memory (NVM) chips. In particular, we experimentally demonstrate a generalized methodology for detecting (i) Integrated Circuit (IC) origin, (ii) recycled or used NVM chips, and (iii) identification of used locations (addresses) in the chip. Our proposed methodology inspects latency and variability signatures of Commercial-Off-The-Shelf (COTS) NVM chips. The proposed technique requires low-cycle ( 100) pre-conditioning and utilizes Machine Learning (ML) algorithms. We observe different trends in evolution of latency (sector erase or page write) with cycling on different NVM technologies from different vendors. ML assisted approach is utilized for detecting IC manufacturers with 95.1 technologies including 6 different manufacturers (9 types of chips).